The present invention relates to dynamic random access memories (DRAMs) including DRAMs embedded in multi-purpose integrated circuits. More specifically, the invention relates to an arrangement and method for storing data to a DRAM.
In the past, DRAMs have provided greater storage density than other integrated circuit memories such as static RAMs (SRAMs), in many cases at a lower cost per stored bit but at a significant penalty to access time. In the past, generally only SRAM, rather than DRAM, has been incorporated into logic integrated circuits for performance reasons. To make DRAMs more desirable for both embedded and stand-alone applications, it has therefore been a goal to decrease the access time to a memory cell within the DRAM. One way to reduce random access cycle time is to shorten the machine cycle, measured as the total time between rising edges of the wordline activation signal.
Conventional DRAMs in which an NFET transistor is used in the memory cell are constrained in that it takes longer to write the storage capacitor of the memory cell to a xe2x80x9c1xe2x80x9d (high voltage state) from a xe2x80x9c0xe2x80x9d (low voltage state) than it takes to write the storage capacitor to a xe2x80x9c0xe2x80x9d from a xe2x80x9c1xe2x80x9d. One solution to this inequality has been to lengthen the machine cycle for writing to accommodate the longest expected write delay, which in this case is the time required to write a xe2x80x9c1xe2x80x9d to a storage capacitor which currently stores a xe2x80x9c0xe2x80x9d, even though many times a storage capacitor will actually be written in less time depending upon the prior state and the state to be stored. This not optimized because it counteracts the goal of reducing DRAM access time by shortening the machine cycle.
Accordingly, the present invention provides an arrangement and method which works toward shortening the machine cycle of a DRAM. With the present invention, a data value is written to a storage capacitor of a memory cell of the DRAM, the data value being stored in the storage capacitor as one of low state and high state. During a first wordline activation cycle, a storage capacitor is preconditioned to a preconditioned voltage level. In a subsequent wordline activation cycle, a new data value is written by writing a low state or a high state to the storage capacitor.
In an aspect of the invention, the wordline is activated in a first wordline activation cycle to begin clearing any previously stored state of the storage capacitor. Then, immediately thereafter, while maintaining the wordline activated, the storage capacitor is preconditioned to a preconditioned voltage level. The wordline is then deactivated. Subsequently, the wordline is activated again during a write cycle to write one of a low state and a high state to the storage capacitor to write a new data value.
Preferably, the first wordline activation cycle includes a read cycle in which any previously stored state is read from the storage capacitor. Preferably, the preconditioned voltage level has a value such that time required to write the high state approximately equals time required to write the low state. More preferably, the preconditioned voltage level is higher than a midpoint between a voltage Vblh indicating high state and a voltage Vlow indicating low state.
In a preferred embodiment, a method is provided for refreshing a once preconditioned storage capacitor of a dynamic random access memory (DRAM) to assist readiness for a subsequent write operation. The method operates upon storage capacitors which have already been preconditioned for writing, but which might not have been written within the interval of a refresh cycle. In some cases, the storage capacitors may have been refreshed once according to the method described here. Therefore, the storage capacitors store a voltage ranging from about the preconditioned voltage level to a high state voltage level (xe2x80x9c1xe2x80x9d) At those current voltage levels, the refresh operation results in such storage capacitors being written to the xe2x80x9c1xe2x80x9d state. Such refresh method integrates well with the herein described preconditioning and writing methods, because it requires no change in the basic read and write cycle components therein. The method includes activating a wordline to read a state currently stored in a storage capacitor, that state being a voltage ranging from about preconditioned voltage level to high state (xe2x80x9c1xe2x80x9d), the state being read as a high state (xe2x80x9c1xe2x80x9d). The storage capacitor is then preconditioned to a preconditioned voltage level immediately thereafter while maintaining the wordline activated. The wordline is then deactivated. Thereafter, during a writeback cycle, the wordline is activated again to store the high state (xe2x80x9c1xe2x80x9d) which was read from the storage capacitor back to the storage capacitor again. In this manner, the storage capacitor is refreshed to high state (xe2x80x9c1xe2x80x9d). At the high state, the storage capacitor is ready to be written during a subsequent write cycle.